(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a silicon dioxide, gate insulator layer, for a metal oxide semiconductor field effect transistor, (MOSFET), device.
(2) Description of Prior Art
The advent of micro-miniaturization, or the use of sub-micron features, for MOSFET devices, have necessitated the use of ultra-thin, gate insulator layers. For example, the use of 0.13 um, (or channel lengths of 0.13 um), technology, results in a projected gate insulator layer, with a thickness in the range of 10 to 20 Angstroms. The use of these ultra-thin gate insulator layers, such as thermally grown silicon dioxide, can present unacceptable leakage rates, during the operation of the 0.13 um MOSFET device. In addition significant, and unacceptable, gate insulator leakage can occur during the standby, or off mode, of the narrow channel length MOSFET device.
This invention will teach a process for forming ultra-thin, silicon dioxide gate insulator layers, in which the leakage rate of the thin silicon dioxide layer is reduced, when compared to counterparts formed without the use of the process described in this present invention. Prior art, such as Gdula et al, in U.S. Pat. No. 3,925,107, describe a post-oxidation, anneal process, which reduces the fixed charge, and fast states, in silicon dioxide, gate layers as thin as 100 Angstroms. However that prior art does not teach the novel process, now presented, allowing ultra-thin, silicon dioxide layers to be used for sub-micron MOSFET devices, featuring reductions in leakage currents, when compared to counterparts fabricated without the benefit of this invention.